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HT48E30
Preliminary
Features
* Operating voltage: * HALT function and wake-up feature reduce power
8-Bit I/O Type MCU (With EEPROM)
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* Low voltage reset function * 23 bidirectional I/O lines (max.) * 1 interrupt input shared with an I/O line * 8-bit programmable timer/event counter with overflow
consumption
* 4-level subroutine nesting * Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
* Bit manipulation instruction * 14-bit table read instruction * 63 powerful instructions * 106 erase/write cycles EEPROM data memory * EEPROM data retention > 10 years * All instructions in one or two machine cycles * In system programming (ISP) * 24/28-pin SKDIP/SOP package
interrupt and 8-stage prescaler
* On-chip crystal and RC oscillator * Watchdog Timer * 204814 program memory ROM (MTP) * 1288 data memory EEPROM * 968 data memory RAM * Buzzer driving pair and PFD supported
General Description
The HT48E30 is an 8-bit high performance, RISC architecture microcontroller device specifically designed for multiple I/O control product applications. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, HALT and wake-up functions, watchdog timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc.
Block Diagram
IN T /P G 0
In te rru p t C ir c u it STACK 4 L e v e ls TM R0 IN T C TM R0C PG0 In s tr u c tio n R e g is te r M U X W DTS DATA M e m o ry W D T P r e s c a le r WDT M U X M U X P r e s c a le r T M R /P C 0 M
U X
fS
YS
P ro g ra m ROM
P ro g ra m C o u n te r
E N /D IS
fS
YS
/4
MP
W DT OSC PAC In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX PA B Z /B Z PBC PG1 PG2 PB PCC OSC2 OS RE VD VS C1 S D S ACC PC PORT C PORT B PB0~PB7 PORT A
PA0~PA7
STATUS
PC0~PC5
D a ta M e m o ry EEPROM
EECR
PGC PG
PORT G
PG0
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Preliminary
Pin Assignment
PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PB4 PB5 1 2 3 4 5 6 7 8 9 10 11 12 PB4 PA3 PA2 PA1 PA0 PB3 PB2 P B 1 /B Z P B 0 /B Z VSS P G 0 /IN T 24 23 22 21 20 19 18 17 16 15 14 13 PB6 PB7 PA4 PA5 PA6 PA7 OSC2 OSC1 VDD RES PC2 P C 0 /T M R PA3 PA2 PA1 PA0 PB3 PB2 P B 1 /B Z P B 0 /B Z VSS P G 0 /IN T P C 0 /T M R PC1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB6 PB7 PA4 PA5 PA6 PA7 OSC2 OSC1 VDD RES PC5 PC4 PC3 PC2
HT48E30
H T48E30 2 4 S K D IP -A /S O P -A
H T48E30 2 8 S K D IP -A /S O P -A
Pad Assignment
PA2 1 PA3 31 PB4 30 PB5 29 PB6 28 PB7 27 PA4 26 PA5 25
T R IM 1 2 3 4 T R IM 2 T R IM 3
24 (0 ,0 ) PA1 5 6 7 8 9 10 11 20 19 12 13 14 15 16 17 18 PA0 PB3 PB2 P B 1 /B Z P B 0 /B Z VSS 23 22 21
PA6 PA7 OSC2 OSC1
VDD RES PC5
PC4
PC3
PC2
PC1
P G 0 /IN T
* The IC substrate should be connected to VSS in the PCB layout artwork.
P C 0 /T M R
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Preliminary
Pad Description
Pad Name I/O Options Pull-high* Wake-up CMOS/Schmitt trigger Input Description
HT48E30
PA0~PA7
I/O
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by options. Software instructions determine the CMOS output or Schmitt trigger or CMOS input (depends on options) with pull-high resistor (determined by 1-bit pull-high options). Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the PB0 or PB1 is selected as buzzer driving outputs, the output signals come from an internal PFD generator (shared with timer/event counter). Negative power supply, ground Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit pull-high options). This external interrupt input is pin-shared with PG0. The external interrupt input is activated on a high to low transition. Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit pull-high options). The timer input are pin-shared with PC0. Schmitt trigger reset input. Active low. Positive power supply OSC1and OSC2 are connected to an RC network or Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.
PB0/BZ PB1/BZ PB2~PB7
I/O
Pull-high* PB0 or BZ PB1 or BZ
VSS
3/4
3/4
PG0/INT
I/O
Pull-high*
PC0/TMR PC1~PC5 RES VDD OSC1 OSC2 Note:
I/O I 3/4 I O
Pull-high* 3/4 3/4 Crystal or RC
* The pull-high resistors of each I/O port (PA, PB, PC, PG) are controlled by a 1-bit option. CMOS or Schmitt trigger option of port A is controlled by a 1-bit option.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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Preliminary
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3V Operating Current (Crystal OSC) 5V IDD2 IDD3 ISTB1 3V Operating Current (RC OSC) 5V Operating Current (Crystal OSC) Standby Current (WDT Enabled) 5V ISTB2 VIL1 VIH1 VIL2 VIH2 VLVR IOL 3V Standby Current (WDT Disabled) 5V Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset Voltage I/O Port Sink Current 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 LVR enabled No load, system HALT 5V No load, fSYS=8MHz 3V No load, system HALT No load, fSYS=4MHz Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz Min. 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 40 10 Typ. 3/4 3/4 0.6 2 0.8 2.5 3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.0 8 20 -4 -10 60 30
HT48E30
Ta=25C Max. 5.5 5.5 1.5 4 1.5 4 5 5 10 1 2 0.3VDD VDD 0.4VDD VDD 3.3 3/4 3/4 3/4 3/4 80 50 Unit V V mA mA mA mA mA mA mA mA mA V V V V V mA mA mA mA kW kW
VDD
Operating Voltage
IDD1
3V VOL=0.1VDD 5V VOL=0.1VDD
IOH
I/O Port Source Current
3V VOH=0.9VDD 5V VOH=0.9VDD 3V
RPH
Pull-high Resistance 5V
3/4 3/4
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Preliminary
A.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V tWDT1 tWDT2 tRES tSST tINT 3V Watchdog Time-out Period (WDT OSC) 5V Watchdog Time-out Period (System Clock) External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width 3/4 3/4 3/4 3/4 Without WDT prescaler 3/4 Wake-up from HALT 3/4 Without WDT prescaler 8 3/4 1 3/4 1 17 1024 3/4 1024 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 Min. 400 400 400 400 0 0 45 32 11 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 90 65 23
HT48E30
Ta=25C Max. 4000 8000 4000 8000 4000 8000 180 130 46 33 3/4 3/4 3/4 3/4 Unit kHz kHz kHz kHz kHz kHz ms ms ms ms tSYS ms tSYS ms
fSYS1
System Clock (Crystal OSC)
fSYS2
System Clock (RC OSC)
fTIMER
Timer I/P Frequency (TMR)
tWDTOSC Watchdog Oscillator Period
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Preliminary
Functional Description
Execution Flow The HT48E30 system clock is derived from either a crystal or an RC oscillator and is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. This pipelining scheme ensures that instructions are effectively executed in one cycle. If an instruction changes the contents of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
T1 T2 T3 T4 T1 T2
HT48E30
incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading into the PCL register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupt, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the current program ROM page. When a control transfer takes place, an additional dummy cycle is required.
S y s te m O S C 2 (R C
C lo c k o n ly ) PC
T3
T4
T1
T2
T3
T4
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *10 0 0 0 *9 0 0 0 *8 0 0 0 *7 0 0 0 *6 0 0 0 *5 0 0 0 PC+2 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *4 0 0 0 *3 0 0 1 *2 0 1 0 *1 0 0 0 *0 0 0 0
Mode Initial Reset External Interrupt Timer/Event Counter Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits S10~S0: Stack register bits @7~@0: PCL bits
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Preliminary
In System Programming In system programming allows programming and reprogramming of HT48EXX microcontroller on application circuit board, this will save time and money, both during development in the lab. Using a simple 3-wire interface, the ISP communicates serially with the HT48EXX microcontroller, reprogramming program memory and EEPROM data memory on the chip. Pin Name Function PA0 PA4 RES VDD VSS SDATA SCLK RESET VDD VSS Description Serial data input/output Serial clock input Device reset Power supply Ground
HT48E30
Certain locations in the program memory are reserved for special usage:
* Location 000H
This area is reserved for program initialization. After a chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the external interrupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
ISP Pin Assignments Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 204814 bits, addressed by the program counter and table pointer.
000H 004H 008H D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Table location
n00H nFFH
P ro g ra m M e m o ry L o o k - u p T a b le ( 2 5 6 w o r d s )
700H 7FFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 4 b its N o te : n ra n g e s fro m 0 to 7
Program Memory
Any location in the program memory space can be used as look-up tables. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 2-bits words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require Table Location
Instruction TABRDC [m] TABRDL [m]
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *10~*0: Table location bits @7~@0: Table pointer bits P10~P8: Current program counter bits
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Preliminary
two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 4 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 4 return addresses are stored). Data Memory - RAM The data memory has a capacity of 1158 bits and is divided into two functional groups: special function registers and general purpose data memory (968). Most are read/write, but some are read only. The special function registers include the indirect addressing registers (R0;00H), timer/event counter (TMR;0DH), timer/event counter control register (TMRC;0EH), program counter lower-order byte register (PCL;06H), memory pointer registers (MP;01H), accumulator (ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register (INTC;0BH), Watchdog Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H, PG;1EH) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PGC;1FH). The remaining space before the 20H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 20H to 7FH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through Rev. 0.00 8
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H PG PGC G e n e ra l P u rp o s e DATA M EM ORY (9 6 B y te s ) PA PAC PB PBC PC PCC TM R TM RC In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C
HT48E30
S p e c ia l P u r p o s e DATA M EM ORY
:U nused R e a d a s "0 0 "
7FH 80H FFH
RAM Mapping memory pointer registers (MP). The control register of the EEPROM data memory is located at [40H] in Bank 1. Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation on [00H] and [02H] access the RAM pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 7-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory in Bank 0, while MP1 can be applied to data memory in Bank 0 and Bank1.
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Preliminary
Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
HT48E30
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine may corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable or disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of the INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a Function
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. Labels C Bits 0
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Unused bit, read as 0 Status Register
AC Z OV PDF TO 3/4 3/4
1 2 3 4 5 6 7
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Register Bit No. 0 1 2 INTC (0BH) 3 4 5 6 7 Label EMI EEI ETI 3/4 EIF TF 3/4 3/4 Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt (1= enabled; 0= disabled)
HT48E30
Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled) Unused bit, read as 0 External interrupt request flag (1= active; 0= inactive) Internal Timer/Event Counter 0 request flag (1= active; 0= inactive) Unused bit, read as 0 Unused bit, read as 0 INTC Register
subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 5 of INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. a b Interrupt Source External Interrupt Timer/Event Counter Overflow Priority Vector 1 2 04H 08H
If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There are 2 oscillator circuits in the microcontroller.
V
DD
OSC1
470pF fS Y S /4 N M O S O p e n D r a in
OSC1
OSC2 C r y s ta l O s c illa to r
OSC2 RC O s c illa to r
System Oscillator All of them are designed for system clocks, namely, external RC oscillator and external Crystal oscillator, which are determined by options. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VDD is required and the resistance must range from 24kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If a Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be connected between OSC1 and OSC2 to obtain a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode and the sys10 January 12, 2004
The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), enable timer/event counter interrupt bit (ETI), enable external interrupt bit (EEI) and enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EEI, ETI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, EIF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. Rev. 0.00
Preliminary
tem clock is stopped, the oscillator still works within a period of 65ms at 5V. The WDT oscillator can be disabled by options to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), instruction clock (system clock divided by 4), determines the options. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by options. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a period of 65ms at 5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 18.6ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.4s at 5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by an external logic. The high nibble and bit 3 of the WDTS are reserved for users defined flags, which can be used to indicate some specified status. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 WDTS Register
S y s te m C lo c k /4
O p tio n S e le c t W DT OSC 8 - b it C o u n te r
HT48E30
The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. But in the HALT mode, the overflow will initialize a warm reset and only the PC and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a HALT instruction. The software instruction includes CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following...
* The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected).
* The contents of the on chip RAM and registers remain
unchanged.
* WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator). * All of the I/O ports maintain their original status.
* The PDF flag is set and the TO flag is cleared.
Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the PC and SP; the others remain in their original status.
W D T P r e s c a le r 7 - b it C o u n te r
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer Rev. 0.00 11 January 12, 2004
Preliminary
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, a regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 (system clock period) to resume to normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status.
HALT
VDD RES S S T T im e - o u t C h ip R eset tS
ST
HT48E30
Reset Timing Chart
V
DD
0 .0 1 m F * 100kW RES 10kW 0 .1 m F *
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
W a rm R eset
Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
RES
W DT
The time-out during HALT is different from other chip reset conditions, since it can perform a warm reset that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO PDF 0 u 0 1 1 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Configuration When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable an SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). The functional unit chip reset status are shown below. PC Interrupt Prescaler WDT Timer/Event Counter Input/Output Ports Stack Pointer, SP 000H Disable Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
Note: u stands for unchanged" To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state.
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Preliminary
The registers status is summarized in the following table. Register TMR TMRC Program Counter MP ACC TBLP TBLH STATUS INTC WDTS PA PAC PB PBC PC PCC PG PGC EECR Note: Reset (Power On) xxxx xxxx 00-0 1000 000H -xxx xxxx xxxx xxxx xxxx xxxx --xx xxxx --00 xxxx --00 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 ---- ---1 ---- ---1 1000 ---* stands for warm reset u stands for unchanged x stands for unknown WDT Time-out RES Reset (Normal Operation) (Normal Operation) xxxx xxxx 00-0 1000 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --1u uuuu --00 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 ---- ---1 ---- ---1 1000 ---xxxx xxxx 00-0 1000 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu --00 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 ---- ---1 ---- ---1 1000 ---RES Reset (HALT) xxxx xxxx 00-0 1000 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --01 uuuu --00 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 ---- ---1 ---- ---1 1000 ----
HT48E30
WDT Time-out (HALT)* uuuu uuuu uu-u uuuu 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --11 uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu ---- ---u ---- ---u uuuu ----
Timer/Event Counter Timer/event counters (TMR) is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or from the system clock by 4. Using the internal clock sources, there are 2 reference time-bases for the timer/event counter. The internal clock source can be selected as coming from fSYS or by options. Using an external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. The timer/event counter can generate PFD signals by using external or internal clock and the PFD frequency is determine by the equation fINT/[2(256-N)]. There are 2 registers related to the timer/event counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the starting value be placed in the timer/event counter preload register and reading TMR retrieves the contents of the timer/event counter. The TMRC is a timer/event counter
control register, which defines some options. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the fINT clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the fINT clock. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bits is 0) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle
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Preliminary
measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the corresponding interrupt services.
HT48E30
In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The overflow signal of the timer/event counter can be used to generate PFD signals for buzzer driving.
Label (TMRC)
Bits
Function Defines the prescaler stages, PSC2, PSC1, PSC0= 000: fINT=fSYS/2 001: fINT=fSYS/4 010: fINT=fSYS/8 011: fINT=fSYS/16 100: fINT=fSYS/32 101: fINT=fSYS/64 110: fINT=fSYS/128 111: fINT=fSYS/256 Defines the TMR active edge of the timer/event counter 0 (0=active on low to high; 1=active on high to low) Enable or disable timer 0 counting (0=disabled; 1=enabled) Unused bit, read as 0 Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC Register
PSC0~PSC2
0~2
TE TON 3/4
3 4 5
TM0 TM1
6 7
(1 /2 ~ 1 /2 5 6 ) fS
YS
8 - s ta g e P r e s c a le r 8 -1 M U X PSC2~PSC0 TM R TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r 1 /2 O v e r flo w to In te rru p t BZ BZ f IN
T
D a ta B u s TM 1 TM 0 T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
Timer/Event Counter
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Preliminary
Input/Output Ports There are 23 bidirectional input/output lines in the microcontroller, labeled from PA to PC and PG, which are mapped to the data memory of [12H], [14H], [16H] and [1EH] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H or 1EH). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PGC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the in t e rn al b u s . Th e l at t er i s p o s s i bl e i n t h e read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 1FH.
HT48E30
After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H or 1EH) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The highest 7-bit of port G are not physically implemented; on reading them a 0 is returned whereas writing then results in no operation. See Application note. There is a pull-high option available for all I/O lines (bit option). Once the pull-high option of an I/O line is selected, the I/O line has a pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. The PB0 and PB1 are pin-shared with BZ and BZ signals, respectively. If the BZ/BZ option is selected, the output signal in output mode of PB0/PB1 will be the PFD signal generated by timer/event counter 0 overflow signal. The input mode always remain in its original functions. Once the BZ/BZ option is selected, the buzzer output signals are controlled by the PB0 data register only.
The I/O functions of PB0/PB1 are shown below. PB0 I/O PB1 I/O PB0 Mode PB1 Mode PB0 Data PB1 Data PB0 Pad Status PB1 Pad Status Note: I I x x x x I I I O x C x D I D O I C x D x D I O I B x 0 x 0 I O I B x 1 x B I O O C C D0 D1 D0 D1 O O B C 0 D 0 D O O B C 1 D B D O O B B 0 x 0 0 O O B B 1 x B B
I input, O output, D, D0, D1 data, B buzzer option, BZ or BZ, x don't care C CMOS output
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Preliminary
V C o n tr o l B it
DD
HT48E30
D a ta B u s
D
PU
Q CK S Q PA PB PC PG 0~PA7 0~PB7 0~PC 5 0
W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D a ta B it Q D CK S Q M U X M U X
W r ite D a ta R e g is te r
PB0 B Z /B Z
( P B 0 , P B 1 O n ly )
BZEN ( P B 0 , P B 1 O n ly )
R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN T fo r P G 0 O n ly
O P0~O P7
Input/Output Ports
The PG0 is pin-shared with INT. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Low Voltage Reset - LVR The HT48E30 provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage is within the range 0.9V~VLVR, such as while changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* Within the low voltage range (0.9V~VLVR), the device
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
V 3 .3 V 2 .4 V
LVR
0 .9 V
remains in their original state until exceeding 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and does not perform a reset function.
* The LVR uses the OR function with the external
Note:
VOPR is the voltage range for proper chip operation at 4MHz system clock.
RES signal to perform chip reset.
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Preliminary
V 5 .5 V
DD
HT48E30
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage has to be maintained in its original state until exceeding 1ms, therefore after a 1ms delay, the device enters a reset mode. EEPROM Data Memory The 1288 bits EEPROM data memory is readable and writable during normal operation. It is indirectly addressed through the control register EECR ([40H] in Bank 1). The EECR can be read and written to only by indirect addressing mode using MP1. Label (EECR) 3/4 CS SK DI DO Bits 0~3 4 5 6 7 Unused bit, read as 0 EEPROM data memory select Serial clock input to EEPROM data memory Serial data input to EEPROM data memory Serial data output from EEPROM data memory Function
CS SK CS
EECR
SK DI DO V
DD
C o n tro l L o g ic and C lo c k G e n e ra to r
A d d r e s s R e g is te r
A d d re s s D e c o d e r M e m o r y C e ll A r r a y 1 K : (1 2 8 8 ) O u tp u t B u ffe r
DI
D a ta R e g is te r
DO Sam e as H T93LC 46
EEPROM Data Memory Block Diagram
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Preliminary
The EEPROM data memory is accessed via a three-wire serial communication interface by writing to EECR. It is arranged into 128 words by 8 bits. The EEPROM data memory contains seven instructions: READ, ERASE, WRITE, EWEN, EWDS, ERAL and WRAL. These instructions are all made up of 10 bits data: 1 start bit, 2 op-code bits and 7 address bits. By writing CS, SK and DI, these instructions can be given to the EEPROM. These serial instruction data presented at the DI will be written into the EEPROM data
HT48E30
memory at the rising edge of SK. During the READ cycle, DO acts as the data output and during the WRITE or ERASE cycle, DO indicates the BUSY/READY status. When the DO is active for read data or as a BUSY/ READY indicator the CS pin must be high; otherwise DO will be in a high state. For successful instructions, CS must be low once after the instruction is sent. After power on, the device is by default in the EWDS state. And, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.
The following are the functional descriptions and timing diagrams of all seven instructions.
tC
SS
CS
tC tS
KH
DS
tS
KL
SK
tC
SH
tD
IS
DI
t D IH V a lid D a ta tP 1
D0
V a lid D a ta tP
D1
DO
EECR A.C. Characteristics Symbol fSK tSKH tSKL tCSS tCSH tCDS tDIS tDIH tPD1 tPD0 tSV tHZ tPR Parameter Clock Frequency SK High Time SK Low Time CS Setup Time CS Hold Time CS Deselect Time DI Setup Time DI Hold Time DO Delay to 1 DO Delay to 0 Status Valid Time DO Disable Time Write Cycle Time Per Word VCC=5V10% Min. 0 250 250 50 0 250 100 100 3/4 3/4 3/4 100 3/4 Max. 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 250 250 250 3/4 2 VCC=2.2V10% Min. 0 500 500 100 0 250 200 200 3/4 3/4 3/4 200 3/4 Max. 1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 500 500 250 3/4 5
Ta=25C Unit MHz ns ns ns ns ns ns ns ns ns ns ns ms
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READ The READ instruction will stream out data at a specified address on the DO. The data on DO changes during the low-to-high edge of SK. The 8 bits data stream is preceded by a logical 0 dummy bit. Irrespective of the condition of the EWEN or EWDS instruction, the READ command is always valid and independent of these two instructions. After the data word has been read the internal address will be automatically incremented by 1 allowing the next consecutive data word to be read out without entering further address data. The address will wrap around with CS High until CS returns to Low. EWEN/EWDS The EWEN/EWDS instruction will enable or disable the programming capabilities. At both the power on and power off state the device automatically entered the disable mode. Before a WRITE, ERASE, WRAL or ERAL instruction is given, the programming enable instruction EWEN must be issued, otherwise the ERASE/WRITE instruction is invalid. After the EWEN instruction is issued, the programming enable condition remains until power is turned off or an EWDS instruction is given. No data can be written into the EEPROM data memory in the programming disabled state. By so doing, the internal memory data can be protected. ERASE The ERASE instruction erases data at the specified addresses in the programming enable mode. After the ERASE op-code and the specified address have been issued, the data erase is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signals for the internal erase, so the SK clock is not required. During the internal erase, we can verify the busy/ready status if CS is high. The DO will remain low but when the operation is over, the DO will return to high and further instructions can be executed. WRITE
HT48E30
The WRITE instruction writes data into the EEPROM data memory at the specified addresses in the programming enable mode. After the WRITE op-code and the specified address and data have been issued, the data writing is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signal for the internal writing, so the SK clock is not required. The auto-timing write cycle includes an automatic erase-before-write capability. So, it is not necessary to erase data before the WRITE instruction. During the internal writing, we can verify the busy/ready status if CS is high. The DO will remain low but when the operation is over, the DO will return to high and further instructions can be executed. ERAL The ERAL instruction erases the entire 1288 memory cells to a logical 1 state in the programming enable mode. After the erase-all instruction set has been issued, the data erase feature is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signal for the erase-all operation, so the SK clock is not required. During the internal erase-all operation, we can verify the busy/ready status if CS is high. The DO will remain low but when the operation is over, the DO will return to high and further instruction can be executed. WRAL The WRAL instruction writes data into the entire 1288 memory cells in the programming enable mode. After the write-all instruction set has been issued, the data writing is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signals for the write-all operation, so the SK clock is not required. During the internal write-all operation, we can verify the busy/ready status if CS is high. The DO will remain low but when the operation is over the DO will return to high and further instruction can be executed.
EECR Control Timing Diagrams
* READ
tC CS
DS
SK DI (1 ) 1 S ta r t b it 1 0 0 AN A0
DO
DX
D0
DX M ode AN DX
1 (X 8 ) A6 D7
* * A d d r e s s p o in te r a u to m a tic a lly c y c le s to th e n e x t w o r d
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* EWEN/EWDS
CS S ta n d b y
HT48E30
SK 0 (1 ) S ta r t b it 0 11=EW EN 00=EW DS
DI
* WRITE
CS tC
DS
V e r ify
S ta n d b y
SK 0 (1 ) S ta r t b it 1 tP
R
DI DO
1
AN
A N -1
A N -2
A1
A0
DX
D0 tS
V
B usy
Ready
* ERASE
CS tC
DS
V e r ify
S ta n d b y
SK 1 (1 ) S ta r t b it 1 tP
R
DI DO
1
AN
A N -1
A N -2
A1
A0 tS
V
B usy
Ready
* ERAL
tC
DS
CS
V e r ify
S ta n d b y
SK 0 (1 ) S ta r t b it 1 tP
R
DI DO
0
1 0
tS
V
B usy
Ready
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* WRAL
tC
DS
HT48E30
CS
V e r ify
S ta n d b y
SK 0 (1 ) S ta r t b it 1 tP
R
DI DO
0
0 1
DX
D0 tS
V
B usy
Ready
EEPROM Data Memory Instruction Set Summary Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Note: Comments Read data Erase data Write data Erase/Write Enable Erase/Write Disable Erase All Write All Start bit 1 1 1 1 1 1 1 Op Code 10 11 01 00 00 00 00 Address A6~A0 A6~A0 A6~A0 11XXXXX 00XXXXX 10XXXXX 01XXXXX Data D7~D0 3/4 D7~D0 3/4 3/4 3/4 D7~D0
X stands for dont care
Options The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper system functioning. Items 1 2 3 4 5 6 7 8 9 CLRWDT instructions: 1 or 2 instructions Timer/event counter clock source: fSYS PA bit wake-up enable or disable PA CMOS or Schmitt input PA, PB, PC, PG pull-high enable or disable (by port) BZ/BZ enable or disable LVR enable or disable System oscillator: RC or crystal Options WDT clock source: WDT oscillator or fSYS/4 or disable
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Application Circuits
V
DD
HT48E30
0 .0 1 m F * 100kW 0 .1 m F
VDD RES
PA0~PA7 PB2~PB7 PC 1~PC 5 V
DD
10kW
0 .1 m F * VSS P B 0 /B Z P B 1 /B Z OSC C ir c u it S e e R ig h t S id e OSC1 OSC2 P C 0 /T M R
R
OSC
470pF C1
OSC1
R C S y s te m O s c illa to r 24kW OSC2 N M O S o p e n d r a in OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
C2 P G 0 /IN T H T48E30 R1
OSC2 OSC
C ir c u it
The following table shows the C1, C2 and R1 value according different crystal values. Crystal or Resonator 4MHz Crystal 4MHz Resonator (3 pin) 4MHz Resonator (2 pin) 3.58MHz Crystal 3.58MHz Resonator (2 pin) 2MHz Crystal & Resonator (2 pin) 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator Note: C1, C2 0pF 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Description Instruction Cycle
HT48E30
Flag Affected
Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Preliminary
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 Description Instruction Cycle
HT48E30
Flag Affected
None None None None None None None None None None None None None
None None
None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
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Preliminary
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator
HT48E30
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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Preliminary
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory
HT48E30
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
HT48E30
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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Preliminary
CPLA [m] Description Complement data memory and place result in the accumulator
HT48E30
Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HALT Description Enter power down mode
HT48E30
This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. PC PC+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
HT48E30
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine
HT48E30
The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
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Preliminary
RLC [m] Description Operation Rotate data memory left through carry
HT48E30
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
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Preliminary
RRCA [m] Description Rotate right through carry and place result in the accumulator
HT48E30
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
HT48E30
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator
HT48E30
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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SZ [m] Description Skip if data memory is 0
HT48E30
If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory
HT48E30
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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Package Information
24-pin SKDIP (300mil) Outline Dimensions
HT48E30
A 24 B 1 13 12
H C D E F G
a
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 1235 255 125 125 16 50 3/4 295 345 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1265 265 135 145 20 70 3/4 315 360 15
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28-pin SKDIP (300mil) Outline Dimensions
HT48E30
A 28 B 1 15 14
H C D E F G
a
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 1375 278 125 125 16 50 3/4 295 330 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1395 298 135 145 20 70 3/4 315 375 15
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24-pin SOP (300mil) Outline Dimensions
HT48E30
24 A
13 B
1
12
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 590 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 614 104 3/4 3/4 38 12 10
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28-pin SOP (300mil) Outline Dimensions
HT48E30
28 A
15 B
1
14
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
Rev. 0.00
41
January 12, 2004
Preliminary
Product Tape and Reel Specifications
Reel Dimensions
T2 D
HT48E30
A
B
C
T1
SOP 24W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
Rev. 0.00
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January 12, 2004
Preliminary
Carrier Tape Dimensions
HT48E30
D
E F
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 24W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.55+0.1 1.5+0.25 4.00.1 2.00.1 10.90.1 15.90.1 3.10.1 0.350.05 21.3
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
Rev. 0.00
43
January 12, 2004
Preliminary
HT48E30
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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January 12, 2004

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